When a calculation is carried out for correlating sampled signals or filtering by a digital signal processor (DSP), etc., it is necessary to access data stored in a prescribed memory region a number of times. The memory region in which the data is stored is called a circular block.
The region of the circular block is represented by an address for the top of the circular block (address within the circular block having the smallest numerical value) (top address) and a numerical value for the capacity of the circular block (block size). When the numerical value obtained by subtracting 1 (one) from the block size is added to the top address, the address for the bottom of the circular block (address having the largest numerical value) (bottom address) is obtained.
The access operation is performed with respect to the circular block for each step value. The value obtained by adding the step value, which may be positive or negative, to a default address, becomes the address to be accessed next. That is, the address as the next access subject (pointer) can be obtained by adding the step value to the default address.
In the following, an explanation will be given regarding the conventional method of address generation in the circular addressing, that is, access with respect to the circular block.
First of all, an explanation will be given for the case in which the step is positive and access is made from the top address to the bottom address. First, the step is added to the default address to derive the first numerical value. This first numerical value becomes the next address. On the other hand, to check whether this first numerical value is larger than the bottom address, the bottom address is subtracted from this first numerical value. But if the difference is .gtoreq.0, the block size is subtracted from the first numerical value to derive a second numerical value. This second numerical value is taken as the next address to achieve circular addressing. When the difference is negative, the first numerical value is taken as the next address.
In the following, an explanation will be given for the case in which the step value is negative, and access is performed from the bottom address to the top address. As in the case in which the step value is positive, at first, the step value is added to a default address to derive the first numerical value. This first numerical value becomes the next address. On the other hand, to check whether this first numerical value is smaller than the top address, the first numerical value is subtracted from this top address. When the result of subtraction of the top address from the first numerical value is .gtoreq.0, the first numerical value is taken as the next address in the circular addressing. But if the result of this subtraction operation is negative, the block size is added to the first numerical value to derive the second numerical value. This second numerical value is taken as the next address in the circular addressing.
By using the method, an address is generated for circular addressing from the top address to the bottom address or from the bottom address to the top address.
On the other hand, there are cases in which it is necessary to repeatedly execute a program stored in the prescribed memory region a prescribed number of times. When access is made to the prescribed memory region (block repeat access), the so-called block repeat addressing method is adopted for addressing. The block repeat addressing is explained below with reference to FIG. 11.
FIG. 11 is a diagram illustrating the configuration of conventional address generating circuit 9 in the block repeat addressing.
As shown in FIG. 11, address generating circuit 9 consists of program counter (PC) 900, comparators 902 and 916, register (END) 904, selector 906, register (START) 908, up counter 910, down counter 912, and block repeat count register (BRCR) 914.
First of all, before implementation of the block repeat operation, the bottom address (end address) of the program for repeated execution is set in register 904, the top address (front address) of the program is set in register 908, and the cycle repetition number is set as the initial value in register 914.
After the start of the block repeat access, an address is generated from program counter 900 for each period of operation. This address is fed to a memory (not shown in the figure) and up counter 910, and it is also output to comparator 902. In up counter 910, one is added (incremented) to the input address, and the result is output to selector 906.
In comparator 902, comparison is made between the address output from program counter 900 and the bottom address stored in register 904 to determine whether they are equal to each other. When comparator 902 determines that the address of program counter 900 and the bottom address are not identical to each other, PC=END signal enters the inactive state (low level), and selector 906 selects the input I0 side, and output is made to program counter 900. That is, when the address in the period of operation is not equal to the bottom address, the address of the period of operation is incremented, and the result is output from program counter 900 as the address of the next period of operation.
When comparator 902 determines that the address output from program counter 900 is equal to the bottom address, PC=END signal enters the active state (high level), selector 906 selects the input I1 side, and output is made to program counter 900. That is, when the address reaches the bottom address, the top address is output from program counter 900 as the address of the next period of operation.
In addition, when PC=END signal enters the active state, in register 914, the cycle repetition number is subtracted (decremented) by one by means of down counter 912, the decremented value is stored, and it is output to comparator 916. That is, each time one series of generated addresses is completed for executing the total region of the block repeat program in the direction from the top address to the bottom address, the cycle repetition number stored in register 914 is decremented.
After the operation is repeated a prescribed number of cycles, the value in register 914 becomes zero. Comparator 916 compares the cycle repetition number stored in register 914 with zero. If they are equal to each other, the inhibiting signal enters the active state (high level). As the inhibiting signal becomes active, address generating circuit 9 completes the block repeat access operation.